Individual VHDL Assignment

This assignment will have you do some hardware design using VHDL. The desired learning outcome is that you demonstrate an ablility to design and implement a small digital logic circuit using VHDL and FPGA synthesis tools. It is intended as a relatively simple design project. If you have had previous VHDL experience, this should be a very easy assignment.

In the VHDL class exercise, you used VHDL to interface to the FPGA board's switches, lights and seven segment display. This assignment will expand on that work.

VHDL Design Assignment

Here are the requirements for this assignment:

1. The system shall display as a hexadecimal digit on a seven-segment display the binary value that was last entered into the system.
   1. The display shall use the set of symbols shown in Table 3-3 of the Spartan 3 Reference Manual.
2. The system shall allow the user to enter a binary value.
   1. The user shall indicate the binary value by setting slide switches 0 through 3.
   2. The system shall enter the binary value when the user depresses pushbutton 0. The system will ignore changes to the slide switches while pushbutton 0 is depressed.
3. The system shall animate the display of the hexadecimal digit.
   1. The animation will be a simple movement of the hexadecimal digit from one seven segment display to the next in a left to right direction. When the rightmost display shows the hexadecimal value, the system shall display the digit on the leftmost display at the next display interval.
   2. The designer will pick the length of time to display the digit on each seven segment display such that the value is easily seen to be on one display at a time.
   3. The system shall freeze the animation on the current display while pushbutton 1 is depressed.

For many of the Computer Engineering students, your prior VHDL experience should make this an easy assignment. If you find the assignment boring, feel free to expand on it after you have implemented the core piece above.

Additional VHDL Information

• VHDL Mini-Reference
• Links to several VHDL tutorials. (You want the VHDL not Verilog tutorials.)

Submission Instructions

Deposit your VHDL design file and UCF constraint file in the myCourses Individual VHDL Project dropbox by the time specified in the course schedule. Name the files abc1234-animation.vhd and abc1234-animation.ucf where abc1234 is your login id. If there is anything that you need to convey to the instructor include a abc1234-readme.txt file in the dropbox. Useful information to put in this file would be interesting aspects of your design, things that you know do not work in the design, or an explanation of what your design does if you expanded this assignment beyond the set of design requirements above.