The Watchdog timer circuit on the Prometheus CPU module provides a means for protecting the CPU and the system in which it is installed against software crashes or hangups. Once the watchdog timer counters are loaded and the circuit is armed, the circuit must be either disarmed or retriggered before time runs out - otherwise a hard reset occurs. In normal operation either an internal sofware retrigger or a hardware retrigger from an external device will continuously retrigger the watchdog timer so that it never resets the system. The circuit can be programmed to drive several interrupt signals (NMI, SCI, SMI) and an external warning signal Watchdog Output (WDO) before reset occurs.
The watchdog timer circuit contains two counters. Counter 1 (WD1) is triggered by the input signal Watchdog In (WDI) or a software trigger. This timer is driven by a 32.768KHz clock and contains a 16-bit divisor. The maximum time delay for counter 1 is 65535 / 32.768KHz = 2 seconds. When WD1 times out, it does several things:
To prevent counter 1 from timing out, either the watchdog timer must be disabled or it must be retriggered. The retrigger may always be performed by a software retrigger command. It may also be performed by an external signal using the input signal WDI (not to be confused with the name of the counter WD1) when hardware retriggering is enabled.
Counter 2 (WD2) is also driven by the 32.768KHz clock, but it contains an 8-bit divisor. Its maximum delay is 255 / 32.768KHz = 7.8 milliseconds. When counter 2 times out, it generates an unconditional hardware reset. Once counter 2 begins counting, the only way to prevent it from timing out and generating a hardware reset is to disable the watchdog timer circuit. Counter 2 is provided to give the external device time to respond to the WDO signal and perform any necessary tasks before the system resets.
The Watchdog timer circuit on the Hercules-EBX CPU module provides a means for protecting the CPU and the system in which it is installed against software crashes or hangups. Once the watchdog timer counters are loaded and the circuit is armed, the circuit must be either disarmed or retriggered before time runs out - otherwise a hard reset occurs. In normal operation either an internal sofware retrigger or a hardware retrigger from an external device will continuously retrigger the watchdog timer so that it never resets the system. The circuit can be programmed to drive the NMI interrupt signal and an external warning signal Watchdog Output (WDO) before reset occurs.
The watchdog timer circuit contains two counters. Counter 1 (WD1) is triggered by the input signal Watchdog In (WDI) or a software trigger. This timer is driven by a 10KHz clock and contains a 16-bit divisor. The maximum time delay for counter 1 is 65535 / 10KHz = 6.5535 seconds. When WD1 times out, it does several things:
To prevent counter 1 from timing out, either the watchdog timer must be disabled or it must be retriggered. The retrigger may always be performed by a software retrigger command. It may also be performed by an external signal using the input signal WDI (not to be confused with the name of the counter WD1) when hardware retriggering is enabled.
Counter 2 (WD2) is also driven by the 10KHz clock, but it contains an 8-bit divisor. Its maximum delay is 255 / 10KHz = 25.5 milliseconds. When counter 2 times out, it generates an unconditional hardware reset. Once counter 2 begins counting, the only way to prevent it from timing out and generating a hardware reset is to disable the watchdog timer circuit. Counter 2 is provided to give the external device time to respond to the WDO signal and perform any necessary tasks before the system resets.
This page was last modified 11:56, 13 Feb 2004.
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